1. Field of the Invention
The present invention generally relates to integrated circuit manufacturing processes and, more particularly to the relative overlay (placement) error inherent in lithographic processes used to align successive lithographic layers on a semiconductor wafer during semiconductor manufacturing.
2. Description of the Related Art
In the practice of semiconductor manufacturing, lithography is used to replicate designed device structures on a target semiconductor wafer, which is typically 125-300 mm in diameter. To achieve this, each device design is decomposed into a series of process steps, each defined by structures of a lithographic pattern or xe2x80x9clevelxe2x80x9d. Current state-of-the-art semiconductor devices require 20-40 of these lithographic levels to achieve desired functionality. Pattern transfer is achieved by first transferring a magnified version of the level to a photomask, wherein the device design is represented by optically opaque regions on an optically transparent substrate. Today""s state-of-the-art photomask consists typically of chromium/chromium oxide opaque regions supported by a quartz substrate. Light of an appropriate wavelength, typically 193 nm-365 nm, is projected through the photomask, through reducing optics, and focused onto the target wafer, which is coated with a photosensitive polymer (photoresist). Photoresist that is exposed to the light is altered with respect to its solubility characteristics, permitting a developer to selectively remove soluble photoresist and leave the desired device pattern on the wafer.
The devices (xe2x80x9cchipsxe2x80x9d) to be created on the wafer vary in size typically from 2 to 25 mm, and are usually arranged at a uniform periodicity across the wafer to substantially cover its surface. Because today""s state-of-the-art lithography equipment uses reducing optics, and optical elements printing larger than about 30 mm square area are impractical, it is impossible to lithographically transfer (xe2x80x9cprintxe2x80x9d) all structures simultaneously across the full wafer. Thus, each level requires multiple exposures to populate the wafer with device patterns completely. This is accomplished by grouping a number of devices per level into a repeating unit, or xe2x80x9cfieldxe2x80x9d, which is sequentially exposed on the wafer surface until all desired device patterns have been completed. Each field may contain between one to hundreds of chips, constrained primarily by how many chips of each size will fit inside the lithographic (optics) exposure field.
To achieve semiconductor device functionality, it is necessary that the placement of the images at the wafer plane of the current lithographic layer, relative to a prior layer, be within a certain tolerance. This relative placement can be referred to as the xe2x80x9coverlayxe2x80x9d. Overlay errors are typically algebraically decomposed into two groups, errors that can be corrected (minimized) by the exposure equipment (xe2x80x9ccorrectablexe2x80x9d or xe2x80x9csystematicxe2x80x9d errors), and errors that are not easily correctable (remaining, or xe2x80x9cresidualxe2x80x9d errors). Overlay is optimized by adjusting tool settings corresponding to the systematic errors. For today""s state-of-the-art exposure systems, correctable errors typically include zeroth order terms (X and Y translation), as well as first-order terms relating to both the exposure field and the wafer as a whole (Magnification, Rotation, and X/Y axis non-orthogonality).
For lithographic levels which require minimum overlay to a prior level, the initial step in the process requires aligning the photomask from the current level to the prior level images on the wafer, exposing the wafer with a plurality of lithographic fields, recording tool overlay settings used for this exposure, and developing the exposed images. To determine the overlay error, specific structures from both the prior level and current level are measured. From these structures, the overlay error between the current and a prior level can be calculated. If the error is larger than the tolerance required for functionality, the photoresist images are removed (xe2x80x9creworkedxe2x80x9d), and improved estimates for tool settings (xe2x80x9ccorrectionsxe2x80x9d) are determined from the original tool overlay settings and the measured errors. This feedback method is repeated until overlay is found to be within tolerances.
Because reworking wafers is costly, it is desirable to avoid multiple iterations/reworks at each lithographic level. A method which predicts tool overlay settings which will produce overlay errors within the acceptable tolerance during each level""s first iteration is thus highly desired.
Silicon wafers are typically processed through the fabricator in physically distinct and uniquely identified groups, and are referred to as xe2x80x9cbatchesxe2x80x9d or xe2x80x9clotsxe2x80x9d. xe2x80x9cLotxe2x80x9d will be used subsequently with this meaning in mind.
Other conventional methods and devices teach aspects of overlay monitoring, such as U.S. Patent Application Publication No. US2001/0016293 (teaches use of current lot data and two sensing systems to detect a first mark and a street line to which subsequent wafers are compared); U.S. Pat. No. 5,894,350 (teaches a two pass method for correcting offset errors comprising shooting a second alignment mark on a resist covered wafer, using light that will not expose the resist, while optically measuring the overlay offset which is fed back for tool correction); U.S. Pat. No. 5,877,861 (teaches an overlay control system in which interlevel and intralevel data is collected and used to generate offsets fed back to the steppers); U.S. Pat. No. 6,269,322 (teaches an overlay process generated using two printed reticle alignment marks and a third virtual alignment mark midway between the two printed marks); U.S. Pat. No. 6,128,070 (teaches monitoring overlay using a plurality of alignment marks on the initial layer of the wafer, and then using a triangle geometric equation for offset errors of subsequent layer""s overlaying alignment marks); U.S. Pat. No. 6,079,256 (teaches a method of measuring registration accuracy using a periodic grating made from a composite of two successive layers of photolithography); U.S. Pat. No. 5,757,507 (teaches monitoring overlay error on product wafers using a test pattern and optical measuring tools); U.S. Pat. No. 4,703,434 (teaches a method of measuring overlay error using optical tools and grating patterns); IBM Technical Disclosure Bulletin Vol. 29, No. 10, March 1987, pp. 4286-87 (teaches alignment marks in each exposure field that are used and a previously calculated theta correction that is applied; and a calculated motion to a best overlay position of a first exposure field that is used to position the wafer and expose the first field); the complete disclosures of which are herein incorporated by reference.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional overlay monitoring systems and methods, the present invention has been devised, and it is an object of the present invention to provide a feedback method which utilizes lithographic exposure field dimensions to predict tool overlay settings. It is another object of the present invention to retrieve the systematic overlay errors for each lot passing through each lithographic process operation. Still, another object of the present invention is to use a feedback sorting criteria to monitor historical tool overlay settings. Yet another object of the present invention is to base the prediction of tool overlay settings on information more specific to the current lot. It is still another object of the present invention to implement a tool overlay setting prediction system in conjunction with any lithographic process tool type. Still another object of the present invention is to reduce cycle time and processing costs associated with integrated circuit chip manufacturing.
In order to attain the objects suggested above, there is provided, according to one aspect of the invention, a system and method of predicting tool overlay settings comprising generating current lot information, generating historical data of previous passes of lots, categorizing (binning) the historical data into discrete lithographic field size ranges, gathering current process tool lithographic field distortion data, and predicting current lot tool overlay settings based on the current lot information and related historical data.
The method monitors the overlay errors for each lot passing through the lithographic process operation. Moreover, the method uses a feedback sorting criteria to monitor the tool overlay settings. Furthermore, current lot information comprises lithographic field dimensions, from which the lithographic field optics distortion data is generated for the current lithographic process tool. Additionally, the historical data comprises the same-bin lithographic field size dimensions of previous lots, which statistically means the data is derived from the same (or similar) bin of like lots, on the current lithographic tool.
There are several benefits of the present invention. First, the present invention provides a system for using a feedback method utilizing lithographic exposure field dimensions to predict tool overlay settings for a lithographic process operation. Additionally, the present invention adds another criteria by which the tool overlay settings of historic lots can be sorted. Moreover, the present invention utilizes historical xe2x80x9clikexe2x80x9d (same-bin) xe2x80x9clotsxe2x80x9d process tool settings to predict current lot tool settings. As well, the present invention utilizes current process tool lithographic field lens distortion data to predict current lot process tool settings. Also, the present invention utilizes historical lithographic exposure field dimensions and associated process tool overlay settings to mathematically predict current lot lithographic process tool settings. A further benefit of the present invention is that it implements a process tool overlay setting prediction method applicable to any lithographic tool utilizing an imaging projection lens. Finally, the present invention reduces cycle time and processing costs associated with integrated circuit chip manufacturing.